Design of Constant Transconductance Reference Circuits for Ultra-Low Power Applications

• Author / Creator

  Lee, Martin

• The semiconductor industry strives to develop ultra-low power circuits and systems because of the ever-increasing consumer demand for more functionality and longer battery life for portable electronic devices. Subthreshold operation brings both reduced power consumption through lower voltage operation and increased power efficiency since the ratio of a transistor’s transconductance to its biasing current (gm/Ids) is maximized in the subthreshold region. A major challenge of operating in subthreshold is the magnified effect of process, voltage and temperature (PVT) variations because of the exponential current-voltage relationship of the transistors. Under PVT variations, a constant transconductance is needed to limit changes to main circuit parameters, such as gain, frequency response and input matching, to ensure devices operate within specifications.

  The conventional method of maintaining a constant transconductance is by using a beta-multiplier. The effects of channel length modulation cause its transconductance to vary significantly with temperature and voltage. The use of cascode current mirrors reduces the channel length modulation effect at the cost of a higher minimum operating voltage, while using operational amplifiers (op-amp) to equalize the drain voltages, does not entirely eliminate the channel length modulation effect because of the temperature-dependent difference in the source voltages. Other existing works proposed to further minimize the issues of channel length modulation by equalizing the drain source voltage or by cancelling out the effects of channel length modulation by using differential signaling. These methods have the drawbacks of increased reliance on external references and precise components or have limited applications while still requiring the use of cascode and op-amps.

  This thesis presents a constant transconductance reference circuit for subthreshold operation that creates a constant transconductance by subtracting two independent transconductance references. By taking the difference between the output currents of the two independent transconductance references, variations over process, voltage and temperature are reduced by minimizing the effects of channel length modulation without relying on op-amps to regulate the drain voltage. The proposed constant transconductance reference is self-contained and developed to work in place of conventional reference circuits, without influencing the characteristics of the core device. The proposed reference is implemented in TSMC’s 65 nm process, and can provide a constant transconductance over a temperature range of -30°C to 120°C, and a supply voltage range of 0.5 to 1.5 V. A maximum variation of ±0.197% transconductance over temperature and ±1.82% transconductance over the supply voltage can be obtained. Through the subtraction, the proposed circuit also shows less process variation against the conventional constant transconductance reference. The proposed constant transconductance reference posts the highest power efficiency (transconductance over power consumption) amongst the reported constant transconductance references up to the date of this writing. At 0.5 V, the constant transconductance reference produces a transconductance of 21.95 μS while consuming 2.06 μW.

• Subjects / Keywords

  • Subthreshold
  • Low power
  • Low voltage
  • temperature compensation
  • Process
  • Constant Transconductance Reference
  • PTAT current
  • CMOS
  • temperature variation
  • PVT variation
  • voltage
  • Beta-multiplier

• Graduation date

  Fall 2020

• Type of Item

  Thesis

• Degree

  Master of Science

• DOI

  https://doi.org/10.7939/r3-1yj2-h908

• License

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