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Spring 2010
The speed of fuzzy controllers implemented on dedicated hardware is adequate for control of any physical process, but too slow for today’s high-complexity data networks. Defuzzification has been the bottleneck for fast implementations due to the large number of computationally expensive...
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Spring 2013
Highly parallel VLSI implementations of low-density parity-check (LDPC) block code decoders have a large number of interconnections, which can result in designs with low logic density. Bit-serial architectures have been developed that reduce the number of wires needed. However, they do not...
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Spring 2011
This thesis is an exploration into the design of configurable analog block (CAB) for field programmable analog arrays (FPAAs) designed in modern complementary metal-oxide-semiconductor (CMOS) technologies. Specifically, this thesis develops a single configurable analog block (CAB) using an...