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Permanent link (DOI): https://doi.org/10.7939/R35D8NR3R

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Accelerated Verification of Integrated Circuits Against the Effects of Process, Voltage and Temperature Variations Open Access

Descriptions

Other title
Subject/Keyword
Integrated circuits
Verification
Simulation
Type of item
Thesis
Degree grantor
University of Alberta
Author or creator
Shoniker, Michael
Supervisor and department
Cockburn, Bruce (Electrical & Computer Engineering)
Han, Jie (Electrical & Computer Engineering)
Examining committee member and department
Moez, Kambiz (Electrical Engineering)
Liang, Hao (Computing Science)
Department
Department of Electrical and Computer Engineering
Specialization
Integrated Circuits & Systems
Date accepted
2015-10-13T08:37:49Z
Graduation date
2016-06
Degree
Master of Science
Degree level
Master's
Abstract
As Moore's Law continues to drive the advancement of new complementary metal-oxide semiconductor (CMOS) technology generations toward feature sizes in the sub 10 nm regime, the role of process, voltage and temperature (PVT) variations have become increasingly important when designing integrated circuits. Very large scale integration (VLSI) designers are challenged to get millions or even billions of transistors to reliably operate over a wide range of possible operating conditions. This is not an easy task. Variations in transistor properties due to the inherent statistical variability of the fabrication process, power supply voltages, and operating temperatures all determine the conditions that affect the behaviour and/or output of an integrated circuit (IC). IC designers commonly model PVT variations as a combination of discretized values that represent the full range of expected operating conditions and are referred to as PVT corners. Designing such a large system of transistors, while ensuring that a high yield of devices will operate correctly, requires designers to consider all possible combinations of PVT corners to determine the worst-case performance of a circuit during the verification process. Traditional verification methods require SPICE level circuit simulations for every possible PVT corner to find the worst-case performance of a circuit, which has become both time consuming and computationally expensive as modern designs can have several thousands of PVT corners. The PVT verification problem can be treated as a mathematical optimization problem. This thesis proposes a verification method that uses a machine learning model and heuristics to determine worst-case PVT corners without the need for simulating all possible combinations. The Rapid PVT Verification (RPV) algorithm that was developed employs a Gaussian process model (GPM) to extract information generated by PVT simulations to create a model of a given circuit's output behaviour. Heuristics are used to further exploit the information provided by the GPM to determine if the global optimum (worst-case) has been found by the algorithm to a certain degree of confidence.
Language
English
DOI
doi:10.7939/R35D8NR3R
Rights
This thesis is made available by the University of Alberta Libraries with permission of the copyright owner solely for the purpose of private, scholarly or scientific research. This thesis, or any portion thereof, may not otherwise be copied or reproduced without the written consent of the copyright owner, except to the extent permitted by Canadian copyright law.
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