Application Specific Analog-to-Digital Converters (ADCs) for Communication Systems

• Author / Creator

  Aurangozeb, .

• To compete with the existing products, hardware manufacturers are required to develop their products with a great focus on smaller area and lower power consumption. The trade-offs between power, area, and the speed of operation play a vital role in the field of integrated circuit design. Therefore, an enormous architectural exploration is required to achieve the targeted specification. For the architectural exploration, a significant amount of different hardware architectures needs to be prepared and analyzed to meet the required specifications under the worst-case scenario. It not only involves many steps but is also a very time-consuming and tedious process.
  In this dissertation, our architectural exploration was to find the suitable hardware architectures for the given communication systems. More specifically, we tried to minimize the power consumption and area of the most power-hungry block such as analog-to-digital converter (ADC) in the given systems. We designed two ADC prototypes for the given communication systems – one for wireline channel equalization and one for digital beamforming (DBF). The proposed architectures along with the application specific ADCs can successfully achieve lower power and decreases the area, that was verified by the measured results from the implemented prototypes.
  
  The first prototype is a variable resolution analog-to-digital converter (ADC) for the wireline transceiver application. The variable-resolution Flash ADC takes advantage of the channel inter symbol interference (ISI) and adjusts the thresholds of the comparators dynamically based on the prediction to cover a significant amount of ADC dynamic range in which the sampled signal can be appeared. By reusing the comparators, the ADC can provide a programmable resolution from 2-bit to 5.5-bit consuming 40 mW to 90 mW, respectively. For timing recovery, a successive-approximation-register-based time-to-digital converter (SAR-TDC) is used which generates a 5-bit timing information that includes 2-bit ISI and 3-bit timing error to achieve a low-latency, and low-jitter timing recovery. Finally, a 3-to-8 programmable tap feed-forward equalizer (FFE) is used to equalize up to 30 dB loss achieving bit error rate (BER) lower than 10^-8. FFE is implemented in an FPGA and the first 3 taps are realized in a look-up table (LUT). Measured power consumption is 130 mW (excluding FFE) from a 1.2 V power supply with active chip area of 0.2025 mm2 in 65 nm technology. Due to programmability on the both ADC resolution and the number of FFE taps according to the channel loss, the receiver enables energy efficiency according to loss compensation.

  The second prototype is a collaborative ADC for the digital beamforming (DBF) application. In the conventional multiple-input and multiple-output (MIMO) DBF, each channel employs an individual ADC. Therefore, power consumption of these ADCs can easily exceed the transceiver power budget for the portable mobile devices. To resolve this, we introduce a collaborative ADC that digitizes multiple channels together rather than digitizing each channel independently. This technique reduces power consumption on an average by 33% compared to the stand-alone ADCs for a 4-channel MIMO receiver. The ADC takes advantage of the channel diversity by distributing the resolution according to channel signal-to-noise ratio (SNR). The collaborative ADC is designed with eight successive-approximation-register (SAR) ADC units each having 6-bit resolution. This performance is compared with 4 channel ADCs with uniform 11 and 9 bits of resolution. It reduces area and power by half and 41% respectively with only 10% degradation of overall signal-to-noise and distortion ratio (SNDR).

• Subjects / Keywords

  • Collaborative ADC
  • PAM-4
  • Wireline Transceiver
  • ADC

• Graduation date

  Spring 2020

• Type of Item

  Thesis

• Degree

  Doctor of Philosophy

• DOI

  https://doi.org/10.7939/r3-qt73-2v66

• License

  Permission is hereby granted to the University of Alberta Libraries to reproduce single copies of this thesis and to lend or sell such copies for private, scholarly or scientific research purposes only. Where the thesis is converted to, or otherwise made available in digital form, the University of Alberta will advise potential users of the thesis of these terms. The author reserves all other publication and other rights in association with the copyright in the thesis and, except as herein before provided, neither the thesis nor any substantial portion thereof may be printed or otherwise reproduced in any material form whatsoever without the author's prior written permission.