Massively Parallel Nonlinear Device-Level Electromagnetic-Thermal Modeling of Power Electronic Apparatus for HVDC Grid Transient Simulation

• Author / Creator

  Lin, Ning

• Multi-terminal DC (MTDC) grid is turning into reality with fast technological advances towards the modular multilevel converter (MMC) and the landmark hybrid DC breaker. The electromagnetic transient (EMT) simulation tools, including the hardware-in-the-loop emulators and off-line EMT-type solvers, play a significant role in the converter design, as well as test of control and protection strategies for the preparation of on-site type tests in the industry. However, the growing scale of the DC grid from two-terminal high-voltage DC (HVDC) transmission to multiple stations has become a severe challenge to the computational capability of transient simulators. Meanwhile, accurate models which provide insight into detailed device behavior are necessary to shorten the design cycle and consequently reduce costs. The performance of power semiconductor switches in a megawatt or even gigawatt converter is a particular concern. Currently, mainstream simulators used for HVDC grid study do not have device-level transient models albeit their actual voltage and current stresses, as well as the junction temperature, should be estimated in the design procedure to avoid unnecessary shutdown which may incur a heavy economic loss. In a trade-off between computation speed and the depth of information, system-level simulation tools, especially the HIL emulators, prefer the former, while other off-line solvers are dedicated to the latter, but they are unable to compute a large HVDC grid since the simulation process is always accompanied by extraordinarily slow speed and frequent termination due to numerical divergence.Therefore, the focus of this research is to implement device-level power semiconductor switch models for power electronic apparatus in the system-level HVDC grid transient simulation which consequently ensures both computation efficiency and high fidelity. Circuit partitioning is an effective approach in splitting the HVDC grid to create a substantial number of sub-circuits that can be proceeded by parallel algorithms, which are another key aspect in the work, where two types of processors, i.e., the field programmable gate array (FPGA) and the graphics processing unit (GPU), are utilized for different scenarios. Three insulated-gate bipolar transistor (IGBT) and its anti-parallel diode models are proposed, i.e., the linearized curve-fitting model, the dynamic curve-fitting model, and the nonlinear behavioral model to cater for various simulation objects of the HVDC grid. With circuit partitioning of the MMC submodules from their arms, real-time execution becomes feasible on the FPGA with a time-step of 500ns for the two curve-fitting models, whilst the results are as accurate as commercial off-line simulation tools and experimental results. A multi-layer architecture in the hardware design is proposed so that at system-level and device-level models run simultaneously under distinct time-steps to ensure a high fidelity of the emulated IGBT behaviors. Similarly, the hybrid HVDC breaker can be represented by a basic unit with a smaller number of nodes after circuit partitioning. Thus, a dramatic hardware resource utilization reduction is achieved, facilitating the deployment of a large MTDC grid on the FPGA.The GPU is investigated for efficient off-line simulation of large-scale MTDC grid. The single-instruction-multiple-thread (SIMT) mode enabled the GPU kernel to launch many threads and compute them concurrently. Therefore, power electronic components having the same attribute are written as one kernel to achieve massively parallel computing architecture. Meanwhile, for efficiency comparison, multi-core CPU program for the MTDC grid is also developed. It is shown that for the entire CIGR´E B4 DC grid system with nonlinear behavioral IGBT/diode models, the GPU can attain up to 134 and 265 times speedup over multi-core CPU parallelism when the half-bridge and full-bridge submodules are employed in the MMC, and the accuracy of the GPU simulation is validated by industrial standard tools such as SaberRD and PSCAD/EMTDC.

• Subjects / Keywords

  • Field Programmable Gate Array
  • High Voltage Direction Current
  • Hybrid HVDC Breaker
  • Modular Multilevel Converter
  • Parallel Processing
  • Real-time Simulation

• Graduation date

  Spring 2019

• Type of Item

  Thesis

• Degree

  Doctor of Philosophy

• DOI

  https://doi.org/10.7939/r3-vggh-4z30

• License

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