Design and Analysis of Approximate Adders and Multipliers

  • Author / Creator
    Liu, Cong
  • Approximate adders have been considered as a potential alternative for error-tolerant applications to trade off some accuracy for gains in other circuit-based metrics, such as power, area and delay. Existing approximate adder designs have shown substantial advantages in improving many of these operational features. However, the error characteristics of the approximate adders still remain an issue that is not very well understood. A simulation-based method requires both programming effort and time-consuming simulations for evaluating the effect of errors. This method becomes particularly expensive when dealing with various sizes and types of approximate adders. As the first contribution of this thesis, a framework based on analytical models is proposed for evaluating the error characteristics of approximate adders. Error features such as the error rate and the mean error distance are obtained using this framework without developing functional models of the approximate adders for time-consuming simulation. As an example, the estimate of peak signal-to- noise ratios (PSNRs) in image processing is considered to show the potential application of the proposed analysis. This analytical framework provides an efficient method to evaluate various designs of approximate adders for meeting different figures of merit in error-tolerant applications. In addition to adders, multipliers are also key arithmetic circuits in many error-tolerant applications such as digital signal processing (DSP). As the second contribution of this dissertation, a novel approximate multiplier with a lower power consumption and a shorter critical path than traditional (accurate) multipliers is proposed for high-performance DSP applications. This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbors for fast partial product accumulation. Different levels of accuracy can be achieved through a configurable error recovery by using different error reduction strategies. These designs use OR gates and the proposed approximate adder for two configurations of the multiplier: approximate multiplier 1 (AM1) and approximate multiplier 2 (AM2). Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared to the Wallace multiplier, a 16 × 16 bit AM1 implemented in a 28-nm CMOS process shows a reduction in delay and power of 20% and up to 69%, respectively. AM2 has a better accuracy compared to AM1 but with a longer delay and higher power. Image processing applications such as image sharpening and smoothing are used to show the quality of the approximate multipliers in error-tolerant applications. It is shown that by utilizing an appropriate error recovery, the proposed approximate multipliers achieve similar processing accuracy as traditional accurate multipliers, but with significant improvements in power and performance. A comparative evaluation of existing approximate multipliers, including the proposed ones, is also presented in this thesis. Monte Carlo simulations are performed to evaluate the error characteristics of these multipliers. Circuit simulations are further run to compare the delay, area and power consumption of these multipliers. The proposed approximate multipliers have high accuracies and lowest power-delay-products among all the designs, while the other designs have at least one major shortcoming in terms of error and/or circuit characteristics. Therefore the proposed designs achieve the best tradeoff between accuracy, delay and power.

  • Subjects / Keywords
  • Graduation date
  • Type of Item
  • Degree
    Master of Science
  • DOI
  • License
    This thesis is made available by the University of Alberta Libraries with permission of the copyright owner solely for non-commercial purposes. This thesis, or any portion thereof, may not otherwise be copied or reproduced without the written consent of the copyright owner, except to the extent permitted by Canadian copyright law.
  • Language
  • Institution
    University of Alberta
  • Degree level
  • Department
    • Department of Electrical and Computer Engineering
  • Specialization
    • Integrated Circuits and Systems
  • Supervisor / co-supervisor and their department(s)
    • Han, Jie (Electrical and Computer Engineering)
  • Examining committee members and their departments
    • Amaral, Nelson J (Computing Science)
    • Cockburn, Bruce (Electrical and Computer Engineering)