Design and Implementation of 60 GHz CMOS Power Amplifiers

• Author / Creator

  Masoumi Farahabadi, Payam

• The availability of an unlicensed 7 GHz bandwidth around 60 GHz offers great potential for establishment of high-data-rate short-range wireless communication links. Although previously left unutilized, recent advances in electronics enable the development of wireless transceivers at millimeter-wave frequencies. Despite offering a large bandwidth, the high signal attenuation caused by oxygen absorption in 60 GHz band requires the wireless transmitters to transmit signals with power as large as 27 dBm, so the receivers can detect greatly attenuated signals. Therefore, the design of power amplifiers capable of generating such large output powers proves to be a major challenge in the development of 60 GHz wireless transceivers, especially if CMOS technology is chosen for implementation of fully integrated 60 GHz wireless systems. In this dissertation, we present new architectures for power combining transformers, as well as new circuit topologies to improve the performance of 60 GHz power amplifiers implemented in CMOS technology. Although CMOS offers a higher level of integration and lower fabrication cost compared to high-speed compound semiconductor technologies, low supply and breakdown voltages, as well as operation near cutoff frequencies of MOSFETs make the design of power amplifier extremely challenging. Optimization of the efficiency/power performance of CMOS power amplifiers operating at millimeter-wave frequencies requires novelty in the design of active/passive structures. An overview on the technological advances and the challenges in millimeter-wave CMOS power amplifiers is presented by comparing previously reported active/passive power combination techniques. A comprehensive analysis and modeling of the matching circuits and on-chip spiral transformers are developed in order to estimate the passive power efficiency of the coupling circuits and power combining transformers. A new area-efficient power-combining configuration is proposed to achieve a high output power per occupied area. A 60 GHz power amplifier is fabricated utilizing the new combining technique with a measured output power of 18.8 dBm. Second we propose a new circuit topology to enable the capability of dual-mode operation. Also, a new enhancement technique is utilized in order to improve the gain-bandwidth product of cascode gain stages. Fabricated in 65 nm technology, the 60 GHz power amplifier could achieve measured maximum power added efficiency of 17.2% while delivering 18.1 dBm output power. Finally, we explore the utilization of a new dual-mode technique in a distributed active transformer power amplifier. A new power amplifier circuit topology and a new DAT layout technique is proposed in order to improve the power added efficiency and output power simultaneously. Fabricated in 65nm CMOS technology, the maximum measured gain of the 60 GHz power amplifier is 22 dB within a wide 3dB bandwidth of 14 GHz. A maximum saturated output power of 19.7 dBm is measured in high-power mode while a high power added efficiency of 25% is achieved.

• Subjects / Keywords

  • Wireless communications
  • CMOS
  • Millimeter Wave
  • Power Amplifier

• Graduation date

  Spring 2016

• Type of Item

  Thesis

• Degree

  Doctor of Philosophy

• DOI

  https://doi.org/10.7939/R3CN6Z94N

• License

  This thesis is made available by the University of Alberta Libraries with permission of the copyright owner solely for non-commercial purposes. This thesis, or any portion thereof, may not otherwise be copied or reproduced without the written consent of the copyright owner, except to the extent permitted by Canadian copyright law.