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Circuits, Architectures and Antenna Design For 5G Wireless Transceivers

  • Author / Creator
    El-Halwagy, Waleed M.

  • The upcoming fifth mobile generation (5G) standard – scheduled to be launched by 2020 – has recently attracted the attention of the industrial and research communities in different fields owing to its promises to achieve higher bandwidth, data rates and support the continuously growing mobile traffic which is beyond what the current fourth mobile generation (4G) resources can afford. Huge efforts are exerted on both the system and hardware levels to shape this new standard expected to provide a paradigm shift in the wireless communications. The limited bandwidth in the sub-6GHz bands motivated the use of the underutilized spectrum in the mm-Wave frequency bands for 5G. However, many challenges are accompanied with building the mm-Wave wireless transceivers. This includes the high path loss experienced by the transmitted/received signal owing to the high frequency propagation which requires a high gain antenna to compensate for. Moreover, on the battery-operated mobile device side, the integrated circuits blocks should provide the required high-performance levels with low power for longer battery life and the high gain antenna should have compact size and high efficiency. This dissertation aims to share in the 5G research by providing solutions and designs to some of the mm-Wave 5G transceivers building blocks, namely; the fractional-N frequency synthesizer serving as the local oscillator (LO) for the transceiver, the analog-to-digital converter (ADC) required for the hybrid beamfoming and the antenna array.For the LO clock generation, two mm-Wave quadrature fractional-N synthesizers were designed and fabricated in the 65-nm CMOS process; a single-stage fractional-N phase locked loop (PLL) and a cascaded fractional-N PLL. Both prototypes achieve good performance over the frequency range from 26-GHz to 32-GHz. First, the single-stage PLL is presented which consumes 35.8-mW while achieving 500-fs jitter. For enhanced performance, the cascaded PLL is then proposed which consumes 26.9-mW and achieves less than 100-fs jitter with -112.6-dBc/Hz phase noise at 1-MHz offset in the fractional-N mode. The single-stage and cascaded PLLs achieve figure-of-merits (FoM) of -230.58-dB and -248.75-dB, respectively. The proposed cascaded PLL FoM outperforms that of the reported state-of-the-art mm-Wave synthesizers making it a suitable candidate for 5G transceivers. For analog-to-digital conversion, two prototypes were designed and fabricated in the 65-nm CMOS process. First, a first-order noise-shaped time-domain ADC is introduced. It employs a successive approximation register time-to-digital converter (SAR-TDC) as a quantizer for higher resolution and lower quantization noise level. In addition, a 1-bit folded VCO is utilized for enhanced VCO linearity. The SAR-TDC achieves 1.15-ps time resolution with peak DNL/INL of 0.64/0.65-LSB and the 1-bit folded VCO improves the VCO linearity from 12% to 0.17%. The enhanced TDC and VCO performances are the key factors for attaining high-performance levels from the ADC. The fabricated 675-MS/s time-domain ADC achieves peak SNDR/SFDR of 79.5/86.4-dB in 10-MHz bandwidth while consuming a total of 11.65-mW. Second, a Nyquist-rate reconfigurable time-based ADC is presented. It employs a reconfigurable TDC that can be configured as a high resolution correlated double sampling SAR-TDC for the high resolution modes or as a Flash-TDC for the high sampling rate modes. The ADC supports continuous sampling rate variations from 100-MS/s to 5-GS/s providing 13- to 5-bits resolution with exponential power scaling from 8.4-mW to 22.3-mW, respectively and FoM ranging from 14.6- fJ/conv to 196-fJ/conv.Finally, a mm-Wave substrate-integrated vertically-polarized electric dipole antenna is presented. The dipole is fabricated using vias in standard PCB process to fit at the mobile device edge featuring wide fan-beam with high HPBW in the elevation plane (HPBWELEV), high gain and high front-to-back radiation ratio (F/B). For enhanced gain, parasitic-vias are added in front of the dipole. To improve HPBW without sacrificing gain, V-shaped split parasitic-vias are employed. A via-fence surrounds the dipole structure to suppress back radiation and enhance F/B. The dipole is connected to a parallel-strip line (PS) which is interfaced to the main SIW feed through a novel SIW-to-PS transition. A single-dipole, 2×1 array, and 4×1 array prototypes were designed and fabricated on the Rogers RO5880 substrate achieving measured HPBWELEV > 133.1º, F/B > 36-dB, cross-polarization < -39.6-dB and 12.61-dBi gain from the 4×1 array with 95.8% radiation efficiency. The low cost, compactness, and good performance of the proposed dipole make it a competing candidate for the future 5G mobile devices transceivers.

  • Subjects / Keywords
  • Graduation date
    Spring 2018
  • Type of Item
    Thesis
  • Degree
    Doctor of Philosophy
  • DOI
    https://doi.org/10.7939/R36H4D56H
  • License
    Permission is hereby granted to the University of Alberta Libraries to reproduce single copies of this thesis and to lend or sell such copies for private, scholarly or scientific research purposes only. Where the thesis is converted to, or otherwise made available in digital form, the University of Alberta will advise potential users of the thesis of these terms. The author reserves all other publication and other rights in association with the copyright in the thesis and, except as herein before provided, neither the thesis nor any substantial portion thereof may be printed or otherwise reproduced in any material form whatsoever without the author's prior written permission.