Engineering Considerations for the Design of High Performance Zinc Oxide Thin Film Transistors

  • Author / Creator
    Ma, Alex M
  • Zinc oxide (ZnO) thin film transistors (TFTs) are garnering significant interest recently due to their unique combination of high optical transparency, moderately high electron mobility, good stability, and compatibility with low temperature processing. If a low temperature processed, high performance ZnO TFT is demonstrated, it can open the way to new applications that are inaccessible for current TFT technologies e.g. flexible and paper electronics. Typically, to enhance TFT performance, improvements in the intrinsic electronic properties of the device materials are needed. However, in this research, the device architecture’s role on TFT performance is investigated in detail. To that end, a bottom-gated ZnO source-gated thin film transistor (SGTFT) that utilizes a gate-controlled Schottky source injection barrier with a ZnO active channel deposited by pulsed laser deposition (PLD) is presented. The ZnO SGTFT exhibits unique capacitance-voltage and transconductance-gate voltage characteristics that give important insight into its device physics. Based on these measurements, it is expected that the SGTFT can offer a new approach to engineering an enhancement-mode ZnO TFT by limiting the device’s off-state current (Ioff) with a source Schottky barrier. Building on these results, a top-gated, drain-offset ZnO SGTFT fabricated entirely using low temperature atomic layer deposition (ALD) is demonstrated. Besides being more compatible with real-world circuit applications, these ZnO SGTFTs exhibit promising device performance featuring a positive threshold voltage (Vth), low subthreshold swing (SS) of 192 mV/decade, high breakdown voltages exceeding 20 V, and a saturation mobility (μsat) of 3.9 cm^2/Vs. Furthermore, the device can be easily adapted for flexible electronics applications due to its low processing temperatures (< 130 deg C). Consequently, the SGTFT device architecture could be an effective means to achieve a high performance ZnO TFT. To better discern the source-and-drain (S/D) contacts’ influence on TFT performance, identical top-gate staggered ALD ZnO TFTs employing symmetrical gold (Au), titanium tungsten (TiW), and ruthenium (Ru) bottom electrodes are studied with emphasis on analysing the metal/ZnO interface. The ZnO TFT’s characteristics are highly influenced by the metallization scheme at the S/D. After correlating the properties of the metal/ZnO interface with TFT electrical measurements, it is found that Au contacts uniquely induce a highly n-doped ZnO film that makes the TFT unable to turn off and the drive current difficult to saturate. On the other hand, TiW contacts form Schottky barriers with the ZnO, restricting carrier injection into the channel, which then reduces the TFT’s on-state current and mobility. The Ru ZnO TFTs exhibit the best overall performance highlighted by extremely low SS values of ~ 89 V/decade, a positive Vth, a high current on-to-off ratio (Ion/off) of > 10^7, and a moderately high μsat of ∼ 1.4 cm^2/Vs. Their excellent TFT characteristics are attributed to an ohmic metal/ZnO junction with limited adsorbed dopants at the metal-ZnO interlayer. Accurate compact models of ZnO TFTs are necessary for implementation into established and emerging applications. In the final section of this research, ZnO TFTs with varying S/D metallization schemes and device layouts are modelled using a gradual channel approximation (GCA)-based direct current (DC) model that considers a gate-enhanced mobility, S/D contact resistance, and a non-constant saturation current (Isat). Compared to a top-gate, staggered TFT with symmetrical bottom Ru S/D electrodes, the on-state performance dramatically increases after changing the drain electrode to Au from Ru due to Au’s lower resistivity and doping effect. When a copper (Cu) Schottky contact is employed for the source, the lower mobility and drive currents indicative of the source-gated effect emerge. Likewise, after removing the gate-to-drain overlap, the drive current and mobility also decrease because of parasitic losses at the channel edge (opposite to the drain). If the gate-to-drain distance (LGD) is increased, space-charge limited current (SCLC) is observed, and the on-state TFT performance further decreases. Thus, a range of TFT characteristics is measured from exploiting only the S/D contacts and drain-side geometry. All these different behaviours are effectively modelled with parasitic elements at the S/D connected in series with an ideal TFT. According to these results, the ZnO TFT’s characteristics can be individually tailored with precise engineering of the device architecture and S/D contact materials.

  • Subjects / Keywords
  • Graduation date
    Spring 2018
  • Type of Item
  • Degree
    Doctor of Philosophy
  • DOI
  • License
    This thesis is made available by the University of Alberta Libraries with permission of the copyright owner solely for non-commercial purposes. This thesis, or any portion thereof, may not otherwise be copied or reproduced without the written consent of the copyright owner, except to the extent permitted by Canadian copyright law.
  • Language
  • Institution
    University of Alberta
  • Degree level
  • Department
  • Specialization
    • Solid State Electronics
  • Supervisor / co-supervisor and their department(s)
  • Examining committee members and their departments
    • Moez, Kambiz (Electrical and Computer Engineering)
    • Goldthorpe, Irene (Electrical and Computer Engineering, University of Waterloo)
    • Cadien, Ken (Chemical and Materials Engineering)
    • Tsui, Ying (Electrical and Computer Engineering)