Design, implementation and testing of a multilevel DRAM with adjustable cell capacity

• Author / Creator

  Xiang, Yunan.

• Subjects / Keywords

  • Memory hierarchy (Computer science)
  • Computer storage devices
  • Random access memory

• Graduation date

  2002

• Type of Item

  Thesis

• Degree

  Master of Science

• DOI

  https://doi.org/10.7939/R3CC0TX9F

• License

  This thesis is made available by the University of Alberta Libraries with permission of the copyright owner solely for non-commercial purposes. This thesis, or any portion thereof, may not otherwise be copied or reproduced without the written consent of the copyright owner, except to the extent permitted by Canadian copyright law.