A quad-channel 8GS/s 6-bit Successive Approximation Register Analog to Digital Converter

• Author / Creator

  Goodarzy, Behdad

• To compete in the growing market of integrated circuit design, designers are required to ideally develop circuits which consume less power, occupy lower area, and have a better performance. Yet, the trade-offs between power, area, and performance set limits for the designers. As a result, extensive research has been done to explore possible architectural advancements or to optimize available architectures in order to improve the performance, power, and area (PPA) characteristics of the designs.

  To keep up with the increasing need for higher bandwidths, optimization of wire-line transceivers has been the target in many researches. In conventional mixed-signal transceivers, most of the equalization techniques were applied to the signal in the analog domain. Moreover, scaling of the CMOS technologies has risen a need for more precise linearity requirements. Thus, ADC-based receivers, providing the chance to conduct equalization in digital domain while benefiting from other advantages of this domain, have become popular over the past years.

  ADC-based receivers include a front-end, the power-hungry ADCs, and digital equalization circuitry. The front-end extends channel's bandwidth, compensates for the loss, and provides copies of the input signal for multiple ADCs - only in time-interleaved structures. Then, one or a set of power-hungry ADCs digitize the signal. In our work, the main focus was to reduce the power consumption of the ADCs and provides a higher bandwidth and linearity (performance), while keeping the area same as in previous designs.

  We improved the structure and optimized the PPA of an ADC-based receiver. First, this work presents a novel multi-branch cascoded buffer. The results of our simulations showed a higher -3dB bandwidth and better linearity compared to conventional buffers. In addition, using this structure may lead to almost perfect compensation for gain mismatch. Although additional circuitry to compensate for the mismatch was not implemented in our work, our simulations have proven the idea. Secondly, the StrongArm-based comparator was optimized to achieve its maximum gain-speed product. Afterward, the condition to optimize the Gain*Speed/Power of the structure was obtained. The optimized comparator proved to be 58% faster and consumed less than 95% of the previous design's power while providing a higher gain. Thirdly, the structure of the digital control block was also technically optimized, operating with the same function, proving to be almost 25% faster and consuming less power.

• Subjects / Keywords

  • ADC
  • SARADC
  • Analog to Digital Converter
  • ADC-based receiver

• Graduation date

  Spring 2023

• Type of Item

  Thesis

• Degree

  Master of Science

• DOI

  https://doi.org/10.7939/r3-njet-8s63

• License

  This thesis is made available by the University of Alberta Libraries with permission of the copyright owner solely for non-commercial purposes. This thesis, or any portion thereof, may not otherwise be copied or reproduced without the written consent of the copyright owner, except to the extent permitted by Canadian copyright law.