An FPGA-Based Acceleration Platform for The Auction Algorithm

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Author / Creator

Zhu, Pengfei
Auction algorithms have been applied in various linear network problems, such as assignment, transportation, max-flow and shortest path problem. The inherent parallel characteristics of these algorithms are well suited for Field-Programmable Gate Array (FPGA) hardware implementation. In this work, we focus on the acceleration of auction algorithms to solve the assignment problem.
Subjects / Keywords
- FPGA
- Auction Algorithm
Graduation date

Fall 2012
Type of Item

Thesis
Degree

Master of Science
DOI

https://doi.org/10.7939/R3JK93
License

This thesis is made available by the University of Alberta Libraries with permission of the copyright owner solely for non-commercial purposes. This thesis, or any portion thereof, may not otherwise be copied or reproduced without the written consent of the copyright owner, except to the extent permitted by Canadian copyright law.

Language

English
Institution

University of Alberta
Degree level

Master's
Department
- Department of Electrical and Computer Engineering
Specialization
- Computer, Microelectronics Devices, Circuits and Systems
Supervisor / co-supervisor and their department(s)
- Hua Li, Department of Mathematics and Computer Science, University of Lethbridge
- Yu (Bryan) Hu, Department of Electrical and Computer Engineering, University of Alberta
Examining committee members and their departments
- Bruce Cockburn, Department of Electrical and Computer Engineering, University of Alberta
- Yu (Bryan) Hu, Department of Electrical and Computer Engineering, University of Alberta
- Zhijun Qiu, Department of Civil and Environmental Engineering, University of Alberta
- Hua Li, Department of Mathematics and Computer Science, University of Lethbridge