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Input Space Partitioning and Other Heuristics for Minimizing the Number of Corner Simulations During Design Verification Open Access


Other title
Design Verification
Black-box Function Optimisation
Gaussian Process Regression
Type of item
Degree grantor
University of Alberta
Author or creator
Oleynikov, Oleg
Supervisor and department
Han, Jie (Department of Electrical and Computer Engineering)
Cockburn, Bruce (Department of Electrical and Computer Engineering)
Examining committee member and department
Liang, Hao (Department of Electrical and Computer Engineering)
Pedrycz, Witold (Department of Electrical and Computer Engineering)
Han, Jie (Department of Electrical and Computer Engineering)
Cockburn, Bruce (Department of Electrical and Computer Engineering)
Department of Electrical and Computer Engineering
Computer Engineering
Date accepted
Graduation date
2017-11:Fall 2017
Master of Science
Degree level
The continuing reduction in the feature sizes of the latest CMOS (Complementary Metal-Oxide-Semiconductor) technologies allow faster, more compact, and more energy-efficient integrated circuits (ICs). On the downside, the performance of each transistor becomes harder and harder to characterise accurately as smaller transistors are more affected by smaller errors during production process. This tendency makes it more difficult for IC designers to perform an important part of the production flow – design verification (DV) – to ensure their circuits will always behave as required by the specifications, and thus ensure a satisfactory yield of the product. The traditional way of doing DV, corner analysis, requires simulating the circuit for random combinations of expected device parameters (i.e., corners) that affect circuit behaviour. When transistors were larger and more predictable, it was sufficient to simulate them at a smaller number of corners, ranging from five to up to, at worst, several dozen. Now, that number can be greater than one thousand. The corners are tested in a simulator, like Simulation Program with Integrated Circuit Emphasis (SPICE), and it takes significant processing power and time to simulate all the corners as required by DV, significantly extending the time for design iterations and IC production. However, it is not strictly required to simulate all the corners. IC designers really only require the worst-case corner, the corner at which the characteristic is the closest to failing the specifications. If it is possible to locate that worst-case corner before every corner has been simulated, a significant amount of time and resources can be saved. Surrogate function modelling techniques, like Gaussian Process Regression (GPR), provide relatively cheap estimates of function values at a set of test points based on the observations from a set of training points. In addition to the estimates, GPR also provides uncertainties in the estimates, which allows judging the confidence of the resulting Gaussian Process Model (GPM) in deciding if the current known maximum is the global maximum. This easily translates to corner analysis, by representing the characteristic of a circuit as a function dependent on the combination of inputs (corners). A previous student, Michael Shoniker, took the first steps in this problem in his Master of Science thesis. This thesis builds on his work by overcoming some weaknesses of Shoniker’s approach, analysing the benchmark datasets, and analysing own generated datasets to learn what output behaviours make circuits difficult to verify.
This thesis is made available by the University of Alberta Libraries with permission of the copyright owner solely for the purpose of private, scholarly or scientific research. This thesis, or any portion thereof, may not otherwise be copied or reproduced without the written consent of the copyright owner, except to the extent permitted by Canadian copyright law.
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