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Design and Evaluation of Stochastic Circuits for FIR Filters and Vector Quantizers Open Access


Other title
FIR Filters
Stochastic Computing
Vector Quantization
Type of item
Degree grantor
University of Alberta
Author or creator
Wang, Ran
Supervisor and department
Jie, Han (Electrical and Computer Engineering)
Cockburn, Bruce F. (Electrical and Computer Engineering)
Examining committee member and department
Elliott, Duncan G. (Electrical and Computer Engineering)
Hossain, Masum (Electrical and Computer Engineering)
Department of Electrical and Computer Engineering
Microsystems and Nanodevices
Date accepted
Graduation date
Master of Science
Degree level
The compact arithmetic units in stochastic computing can potentially lower the implementation cost with respect to silicon area and power consumption. In addition, stochastic computing provides inherent tolerance of transient errors at the cost of a less efficient signal encoding. Much effort has been put into stochastic circuit designs for application-specific and general-purpose computation. However, the accuracy issue of these stochastic implementations still remains to be understood with respect to appropriate sequence lengths. As the first part of this thesis, the performance of stochastic arithmetic elements (such as stochastic adders, multipliers and absolute subtractors) and a stochastic sum-ofproducts (SOP) circuit are investigated and compared. Due to the long sequences used in the stochastic implementations, the stochastic circuits are not competitive in terms of throughput per area (TPA) or energy per operation (EPO) compared with conventional binary circuits. These stochastic arithmetic elements can be used as basic components in two useful applications: finite impulse response (FIR) filters and vector quantization (VQ) for image compression. FIR filters are key elements in digital signal processor (DSP) due to their linear phasefrequency response. Two novel stochastic FIR filter designs are proposed based on regular or simplified multiplexers. The performance of stochastic and conventional binary FIR filters are implemented using an industrial 28-nm cell library. Silicon area, power and maximum clock frequency were obtained to allow an evaluation of TPA and EPO. Required stochastic sequence lengths are determined by matching the performance of the proposed stochastic FIR filters with that of the conventional binary FIR filter. Different signal resolutions were investigated with the goal of finding the break-even point between the stochastic and binary implementations by criteria such as the TPA and EPO. For equivalent filtering performance, the stochastic FIR filters underperform the conventional binary design in terms of TPA and EPO, although the stochastic design shows a better graceful degradation in performance with a significant reduction in energy consumption. A detailed analysis is performed to evaluate the accuracy of stochastic FIR filters and to determine the required stochastic sequence length. The fault-tolerance of the stochastic design is compared with that of the binary circuit using triple modular redundancy (TMR). The stochastic designs are more reliable than the conventional binary design and its TMR implementation with unreliable voters, but they are less reliable than the binary TMR implementation when the voters are fault-free. Unlike the FIR filters for which accuracy is more critical, VQ is a general data compression technique that can tolerate some loss of information. The VQ technique has a simply scalable implementation complexity and potentially high compression rate. A stochastic implementation of VQ is proposed and evaluated against corresponding conventional binary designs. The effect of varying the stochastic sequence length is studied with respect to TPA and EPO. The stochastic implementations are shown to have higher EPOs than the conventional binary implementations due to their long latencies. For the stochastic implementations using errors measured by the L1 norm, squared L2 norm or 3rd law. When a shorter encoding sequence with 512 bits is used in exchange for lower quality performance, the TPA is about 1.16 to 2.60 times that of the binary implementation with the same compression quality. Thus, the stochastic implementation outperforms the conventional binary design in terms of TPA for a reduced compression quality. By exploiting the progressive precision feature of a stochastic circuit, a readily scalable processing quality can be simply attained by halting the computation after different numbers of clock cycles.
Permission is hereby granted to the University of Alberta Libraries to reproduce single copies of this thesis and to lend or sell such copies for private, scholarly or scientific research purposes only. The author reserves all other publication and other rights in association with the copyright in the thesis and, except as herein before provided, neither the thesis nor any substantial portion thereof may be printed or otherwise reproduced in any material form whatsoever without the author's prior written permission.
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