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Low Power Digital Receivers for Multi-Gb/s Wireline/Optical Communication

  • Author / Creator
    Hossain, A K M Delwar
  • As the gate length scaling continues to less than 10nm, digital performances of integrated circuits (IC) continue to improve at a faster rate than their analog performances. This naturally leads to a trend where traditional high-speed mixed signal transceivers have to be replaced by their digital counterparts. For a wireline receiver, this means replacing traditional analog mixed signal equalizers with digital equalization techniques while still fitting within challenging power budget. Similarly, traditional optical receivers use analog mixed signal techniques to solve data dependent DC offset, burst mode timing recovery, etc. This work introduces fully digital techniques to address these challenges to design compact, low power digitally-enhanced optical receivers. The first receiver architecture of this dissertation describes the design technique of energy-efficient sequence detection and equalization without the use of any ADC and DSP. This scheme takes advantage of the inter-symbol-interference (ISI) in the channel to reconstruct the time domain bit sequence. It is the most power efficient digital receiver reported to date. It improves power efficiency i.e. power consumed per bit by 2.5X and power consumed per bit per dB channel loss by 2.65X of the state-of-art. The second receiver takes the architecture of the first receiver and modifies it to introduce data trace-back. This is the first-time implementation of data trace-back in SerDes. The data trace-back improves noise immunity and the voltage margin of the system. The added data trace-back with the decision feedback equalization (DFE) improved BER from 10-10 (DFE only) to 10-12. The third receiver architecture describes a low power 7-10 Gb/s burst mode DC-coupled receiver for photonic switch networks. The concurrent operation of DC and timing recovery implies low latency in burst mode receivers. DC is recovered using SAR (successive approximation register) logic within 6 cycles of 1/8th of data rate clock, which is 6.5X improvement from the current state-of-art. It consumes only 32.7 mW during runtime.

  • Subjects / Keywords
  • Graduation date
    2017-06
  • Type of Item
    Thesis
  • Degree
    Master of Science
  • DOI
    https://doi.org/10.7939/R3WH2DS61
  • License
    This thesis is made available by the University of Alberta Libraries with permission of the copyright owner solely for non-commercial purposes. This thesis, or any portion thereof, may not otherwise be copied or reproduced without the written consent of the copyright owner, except to the extent permitted by Canadian copyright law.
  • Language
    English
  • Institution
    University of Alberta
  • Degree level
    Master's
  • Department
    • Department of Electrical and Computer Engineering
  • Specialization
    • Integrated Circuits and Systems
  • Supervisor / co-supervisor and their department(s)
    • Masum Hossain, Department of Electrical and Computer Engineering
  • Examining committee members and their departments
    • Kambiz Moez, Department of Electrical and Computer Engineering
    • Duncan Elliott, Department of Electrical and Computer Engineering