Digitally Enhanced Information Efficient Wireline Signaling

• Author / Creator

  Dey, Shovon

• With the increase in integrated functionalities within a single chip due to the continuous scaling of the gate length of transistors, off-chip bandwidth must catch up to make the increased functionalities accessible. The future of off-chip bandwidth might reach 100 Tbps according to ITRS (International Technology Roadmap for Semiconductors). But the electrical channel introduces latency and frequency-dependent attenuation which causes significant hindrance towards achieving higher off-chip bandwidth. Power efficiency is also one of the main concerns while working in a high-speed environment. This work introduces several digital techniques that increase the power and bandwidth efficiency of High-Speed Wireline systems.
  The first work in this dissertation explains a digital technique that uses a generated alternated sequence to detect and correct any burst errors in Decision Feedback Equalization (DFE). This scheme takes advantage of the correlation between Inter-Symbol Interferences (ISI) to correct propagated error in DFE. The proposed architecture achieves a BER of less than 10-12 while working at 16 Gbps.
  The second work in this thesis describes a complete low power 16 Gbps SerDes Transceiver with 0.0375 pJ/Bit link efficiency while transmitting 90% sparse data. In this work, the transmitted bits were transition encoded which results in a significant power efficiency improvement while working with random as well as sparse data. The receiver architecture includes a CTLE (Continuous Time Linear Equalizer) and the rest of the architecture is similar to 1-tap speculative DFE.
  The third work describes a binary search ADC (Analog-to-Digital Converter) with a novel digital interpolation technique. Concurrent Binary Search was used in this work to reduce the conversion time of the SAR (Successive Approximation Register) type ADC. The 4-way time-interleaved architecture achieved 4 GS/s speed with an 8-bit resolution having 39.56 dB SNDR and 48.21 dB SFDR at the Nyquist frequency.

• Subjects / Keywords

  • ECE
  • ADC
  • DFE
  • Wireline

• Graduation date

  Fall 2020

• Type of Item

  Thesis

• Degree

  Master of Science

• DOI

  https://doi.org/10.7939/r3-kh9n-dk50

• License

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