Stochastic Computational Approaches for the Reliability Evaluation of Nanoelectronic Circuits

• Author / Creator

  Chen, Hao

• Reliability is fast becoming a major concern due to the nanometric scaling of CMOS technology. This thesis work initially presents novel computational models based on stochastic computation; in these models, probabilities are encoded in the statistics of random binary bit streams. A computational approach using the stochastic models is then proposed for the reliability evaluation of logic circuits. As it takes into account signal correlations and evaluates the joint reliability of multiple outputs, this approach accurately determines the reliability of a circuit; its precision is only limited by the random fluctuations inherent in the representation of the random binary bit streams. The proposed stochastic approach has a linear computational complexity and is therefore scalable for large circuit analysis. Extensive simulation results demonstrate the accuracy, scalability and execution simplicity of the proposed approach.

• Subjects / Keywords

  • CMOS Scaling
  • IC Reliability

• Graduation date

  Spring 2012

• Type of Item

  Thesis

• Degree

  Master of Science

• DOI

  https://doi.org/10.7939/R3K71X

• License

  This thesis is made available by the University of Alberta Libraries with permission of the copyright owner solely for non-commercial purposes. This thesis, or any portion thereof, may not otherwise be copied or reproduced without the written consent of the copyright owner, except to the extent permitted by Canadian copyright law.