Low-power Error-tolerant Digital Logic Circuit Design

• Author / Creator

  Li, Yufeng

• As semiconductor process minimum linewidths have been scaled down to nanometers, digital computing circuits have become more and more complex. Meanwhile, these hardware circuits are required to be easily integrated into portable devices, be reliable even in a noisy environment, and have low power consumption to save energy. In other words, area, reliability and power consumption are three inevitable issues existing in modern Very-large-scale Integration (VLSI) designs. Therefore, researchers have focused effort on the low-power error-tolerant designs and have tried to find a better balance among the three issues, as sometimes there has to be a trade-off between one and another. Breakthroughs are sought in transistor-level designs, gate/cell-level designs and system-level designs. In this thesis, some new gate/cell-level designs and system-level designs are presented, including Markov random field (MRF)-based complementary dual modular redundancy (CDMR), discrete cosine transform (DCT) implementations based on MRF-stochastic logic, coding-based partial MRF (CPMRF) circuit design, and probabilistic-based complementary (PC) logic gate design.
  MRF-based CDMR overcomes the large area cost and the vulnerability of the voting circuits in the triple modular redundancy (TMR) configuration and mitigates the effect of soft errors based on the MRF theory and the idea of the combination of stable logic signals. In the CDMR, the proposed two-stage voting circuit contains an MRF feedback structure in the first stage and a merging unit in the second stage. Compared with previous designs, it helps the whole system save the area of one module while lowering the large power consumption with a low error rate.
  DCT implementation based on MRF-stochastic logic combines MRF theory and stochastic logic to simplify the hardware without losing high noise immunity for the DCT system in nanoscale conditions. MRF-based gate groups are designed to save area overhead for stochastic adders and multipliers used in one-dimensional DCT (1D-DCT). The proposed design not only achieves better noise-immunity but also saves hardware and power cost when compared with a master-slave version of the design.
  CPMRF circuit design summarizes a general mapping method for logic operations. Unlike the conventional MRF designs, CPMRF gate pairs can easily achieve multi-logic operations by sharing a common MRF network. The coding structure complements the loss of the energy and strengthens the stability of the logic “1” and “0” states. An 8-bit carry lookahead adder (CLA) is built to measure the performance of the proposed method. It has relatively high noise immunity with low hardware cost and low power consumption, which corresponds to the theoretical analysis.
  PC logic gate design separates logic “1” and “0” signals into either robust bits and weak bits from the perspective of probability. The design tolerates errors in terms of probability. By only choosing robust bits, the proposed logic gates can generate high quality output signals. Also, a general mapping rule is deduced to allow the idea to be easily implemented automatically within the existing Electronic Design Automation (EDA) flows.

• Subjects / Keywords

  • Error tolerance
  • Logic gates
  • Low power
  • Markov Random Field

• Graduation date

  Fall 2019

• Type of Item

  Thesis

• Degree

  Doctor of Philosophy

• DOI

  https://doi.org/10.7939/r3-m9wz-dx61

• License

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