ERA Banner
Download Add to Cart Share
More Like This
  • http://hdl.handle.net/10402/era.29306
  • Digit-Online LDPC Decoding
  • Marshall, Philip A.
  • English
  • Low-Density Parity Check (LDPC) Codes
    Forward Error Correction (FEC)
    Iterative Decoder Architecture
    Message-Passing Decoding
    Digit-Online
    Digit-Serial Arithmetic
  • Oct 26, 2012 12:04 PM
  • Thesis
  • English
  • Adobe PDF
  • 669937 bytes
  • Highly parallel VLSI implementations of low-density parity-check (LDPC) block code decoders have a large number of interconnections, which can result in designs with low logic density. Bit-serial architectures have been developed that reduce the number of wires needed. However, they do not fully realize the potential for deeply pipelined serial data processing. Digit-online arithmetic allows operations to be performed in a serial, digit-by-digit manner, making it ideal for use in implementing a digit-serial LDPC decoder. Digit-online circuits for the primitive operations required for an offset min-sum LDPC decoder are simple, and allow deep pipelining at the digit level. A new hardware architecture for LDPC decoding is demonstrated, using redundant notation to allow for most-significant-digit-first processing of log-likelihood-ration (LLR) messages at all nodes. We examine the effect of changing the precision of LLRs on the throughput, area and energy efficiency of bit-parallel and digit-online decoders for the irregular WiMAX rate 3/4A length-1056 code. Both single-frame and frame-interlaced decoding are considered. To examine post-layout and code size effects, 9-bit bit-parallel and digit-online decoders for the irregular WiMAX rate 3/4A and rate 5/6 codes are compared for code lengths varying from 576 to 2304. Post-layout decoder results are presented for the (2048,1723) 10GBASE-T LDPC code in a general-purpose 65-nm CMOS technology. The decoder requires a core area of 10.89 mm^2 and operates at a clock frequency of 980 MHz. Decoding can be done with a message precision of 4 or 10 bits. With 4-bit precision, the decoder achieves a coded throughput of 82.8 Gbit/s, 73% higher than the state-of-the-art published decoder. We extend the message precision of previously published 10GBASE-T decoders from 4-5 bits to 10 bits. In this 10-bit mode we achieve a throughput of 41.8 Gbit/s, only 12% less than the state-of-the-art 4-bit decoder.
  • Marshall, P., Gaudet, V. and Elliott, D. (2012) “Effects of Varying Message Precision in Digit-online LDPC Decoders”. IEEE Workshop on Signal Processing Systems (SiPS) 2012, 6 pages accepted for publication
    Marshall, P., Gaudet, V. and Elliott, D. (2011) “Deeply Pipelined Digit-Serial LDPC Decoding”. IEEE Trans. on Circuits and Systems I: Regular Papers, 11 pages in print. DOI: 10.1109/TCSI.2012.2206461
  • Doctoral
  • Doctor of Philosophy
  • Department of Electrical and Computer Engineering
  • Computer, Microelectronic Devices, Circuits and Systems
  • Spring 2013
  • Elliott, Duncan (Electrical and Computer Engineering)
    Gaudet, Vincent (Electrical and Computer Engineering)
  • Cockburn, Bruce (Electrical and Computer Engineering)
    Doucette, John (Mechanical Engineering)
    Thornton, Mitchell (Southern Methodist University, Dallas, Texas, USA)