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Permanent link (DOI): https://doi.org/10.7939/R35M62D8Z

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Real-Time Hardware Emulation of a Multifunction Protection System Open Access

Descriptions

Other title
Subject/Keyword
multifunction protection system
Type of item
Thesis
Degree grantor
University of Alberta
Author or creator
Wang, Yifan
Supervisor and department
Dinavahi, Venkata (Electrical and Computer Engineering)
Examining committee member and department
Nowrouzian, Behrouz (Electrical and Computer Engineering)
Han, Jie (Electrical and Computer Engineering)
Dinavahi, Venkata (Electrical and Computer Engineering)
Department
Department of Electrical and Computer Engineering
Specialization
energy system
Date accepted
2013-11-22T14:49:22Z
Graduation date
2014-06
Degree
Master of Science
Degree level
Master's
Abstract
The need for high-speed multifunction protective relays in modern power systems is growing. A relay's fast response and reliable operation to clear faults is essential, especially in the context of smart grids. This research proposes a low-latency hardware digital multifunction protective relay on the Field Programmable Gate Array (FPGA). Taking advantage of inherent hard-wired architecture of the FPGA, the proposed hardware relay design is paralleled and fully pipelined to achieve low latencies in various relay modules which are developed in hardware description language. This low-latency feature allows fast operation and data throughput to reach higher computational efficiency. In addition, the parallelism and the hardwired architecture of the FPGA make the design more reliable in computation than the sequential software-based numeric relay. The case studies demonstrate the effectiveness of the multifunction hardware relay.
Language
English
DOI
doi:10.7939/R35M62D8Z
Rights
Permission is hereby granted to the University of Alberta Libraries to reproduce single copies of this thesis and to lend or sell such copies for private, scholarly or scientific research purposes only. Where the thesis is converted to, or otherwise made available in digital form, the University of Alberta will advise potential users of the thesis of these terms. The author reserves all other publication and other rights in association with the copyright in the thesis and, except as herein before provided, neither the thesis nor any substantial portion thereof may be printed or otherwise reproduced in any material form whatsoever without the author's prior written permission.
Citation for previous publication
Y. Wang, V. Dinavahi, "Low-Latency Distance Protective Relay on FPGA," IEEE Transactions on Smart Grid, vol.PP, no.99, pp.1-10

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