ERA

Download the full-sized PDF of Simulation of quantization noise effects on the performance of a wireless preamble detector and demonstration of a functional FPGA prototypeDownload the full-sized PDF

Analytics

Share

Permanent link (DOI): https://doi.org/10.7939/R32Q60

Download

Export to: EndNote  |  Zotero  |  Mendeley

Communities

This file is in the following communities:

Graduate Studies and Research, Faculty of

Collections

This file is in the following collections:

Theses and Dissertations

Simulation of quantization noise effects on the performance of a wireless preamble detector and demonstration of a functional FPGA prototype Open Access

Descriptions

Other title
Subject/Keyword
Communication
FPGA
Preamble
Type of item
Thesis
Degree grantor
University of Alberta
Author or creator
Son, Eric Tien Tze
Supervisor and department
Gaudet, Vincent (Electrical and Computer Engineering)
Examining committee member and department
Schlegel, Christian (Computing Science )
Cockburn, Bruce (Electrical and Computer Engineering)
Department
Electrical and Computer Engineering
Specialization

Date accepted
2009-10-02T15:26:52Z
Graduation date
2009-11
Degree
Master of Science
Degree level
Master's
Abstract
This thesis describes the implementation of the physical layer for an experimental low-power wireless communication device. The system utilizes differential coherent correlation and threshold-based detection to produce a robust random-access packet-based communications protocol. Prior to implementing the system in hardware, the detection algorithm was rigorously simulated with a software model in C. The simulations revealed the tradeoffs between the packet miss performance and different system parameters such as input bit precision and threshold value. Having determined a suitable configuration, the detection algorithm was implemented on an FPGA platform. The focus of the FPGA design was on throughput and resource utilization. The final system utilizes approximately 6% of the slices available on a Xilinx Virtex II XC2V8000 FPGA and has a throughput of about 5 MChips/Second.
Language
English
DOI
doi:10.7939/R32Q60
Rights
License granted by Eric Son (eson@ualberta.ca) on 2009-09-30T17:43:01Z (GMT): Permission is hereby granted to the University of Alberta Libraries to reproduce single copies of this thesis and to lend or sell such copies for private, scholarly or scientific research purposes only. Where the thesis is converted to, or otherwise made available in digital form, the University of Alberta will advise potential users of the thesis of the above terms. The author reserves all other publication and other rights in association with the copyright in the thesis, and except as herein provided, neither the thesis nor any substantial portion thereof may be printed or otherwise reproduced in any material form whatsoever without the author's prior written permission.
Citation for previous publication

File Details

Date Uploaded
Date Modified
2014-04-29T18:58:02.512+00:00
Audit Status
Audits have not yet been run on this file.
Characterization
File format: pdf (Portable Document Format)
Mime type: application/pdf
File size: 1728226
Last modified: 2015:10:12 15:13:53-06:00
Filename: Son_Eric_Fall 2009.pdf
Original checksum: 737591f6119e70408b5398298c207017
Well formed: true
Valid: true
File author: eson
Page count: 81
File language: en-US
Activity of users you follow
User Activity Date