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Permanent link (DOI): https://doi.org/10.7939/R3CC0TX9F

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Design, implementation and testing of a multilevel DRAM with adjustable cell capacity Open Access

Descriptions

Other title
Subject/Keyword
Random access memory.
Memory hierarchy (Computer science)
Computer storage devices.
Type of item
Thesis
Degree grantor
University of Alberta
Author or creator
Xiang, Yunan.
Supervisor and department
Examining committee member and department
Department
Department of Electrical & Computer Engineering
Specialization

Date accepted
2002
Graduation date

Degree
Master of Science
Degree level
Master's
Abstract

Language
English
DOI
doi:10.7939/R3CC0TX9F
Rights
Permission is hereby granted to the University of Alberta Libraries to reproduce single copies of this thesis and to lend or sell such copies for private, scholarly or scientific research purposes only. The author reserves all other publication and other rights in association with the copyright in the thesis and, except as herein before provided, neither the thesis nor any substantial portion thereof may be printed or otherwise reproduced in any material form whatsoever without the author's prior written permission.
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