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Permanent link (DOI): https://doi.org/10.7939/R3QV3CG3D

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Fabrication, Characterization, and Simulation of Highly-Scaled III-V MOS Devices Open Access

Descriptions

Other title
Subject/Keyword
InP
MOSFETs
ZrO2
Gate oxides
GaN
PEALD
MOS capacitors
Type of item
Thesis
Degree grantor
University of Alberta
Author or creator
Rezazadeh, Vallen G
Supervisor and department
Dr. Douglas Barlage (Electrical and Computer Engineering)
Examining committee member and department
Dr. Mani Vaidyanathan (Electrical and Computer Engineering)
Dr. Douglas Barlage (Electrical and Computer Engineering)
Dr. Kenneth Cadien (Chemical and Materials Engineering)
Department
Department of Electrical and Computer Engineering
Specialization
Solid-State Electronics
Date accepted
2017-01-20T09:26:54Z
Graduation date
2017-06:Spring 2017
Degree
Master of Science
Degree level
Master's
Abstract
To enable scalable MOSFET technology in III-V semiconductor platforms, high quality semiconductor-oxide interfaces are essential. In this work, the role of surface reactions in the oxide deposition process is examined, with the objective of optimizing the thermodynamics of the semiconductor-oxide interface. A novel low-temperature plasma-enhanced atomic layer deposition (PEALD) technique was applied to deposit nanoscale high-k dielectrics on several III-V substrates, including InP, GaAs, InAs, and GaN. Approximately 7 nm of ZrO2 was grown and patterned to form MOSCAP structures, which were subsequently analyzed through electrical characterization to evaluate dielectric and interface quality. The oxide films fabricated were found to have interface trap densities ranging from 1010-1013 eV-1cm-2, and showed high capacitance densities (~2.5 μF/cm2). GaN and InP MOSCAPs with ZrO2 dielectric layers were found to have gate currents in line with direct tunneling phenomena and MOS mobilities approaching that of doped bulk semiconductors. Scaled InP MOSFET devices using these experimental oxide results were also simulated using improved device structures, with the aim of demonstrating optimal parameters for effective reduction of short-channel effects. These devices demonstrated high performance for various scaled gate lengths, with FinFET structures showing excellent frequency response at the 7 nm process node.
Language
English
DOI
doi:10.7939/R3QV3CG3D
Rights
This thesis is made available by the University of Alberta Libraries with permission of the copyright owner solely for the purpose of private, scholarly or scientific research. This thesis, or any portion thereof, may not otherwise be copied or reproduced without the written consent of the copyright owner, except to the extent permitted by Canadian copyright law.
Citation for previous publication
Rezazadeh, Vallen, et al. "Defect Characterization of PEALD High-k ZrO2 Films Fabricated on III-V Materials." IEEE Transactions on Semiconductor Manufacturing 29.4 (2016): 355.

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