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Permanent link (DOI): https://doi.org/10.7939/R3PZ51V3P

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Design and Optimization of Decoders for Low-Denisty Parity Check Codes Synthesized from the OpenCL Specifications Open Access

Descriptions

Other title
Subject/Keyword
OpenCL
LDPC
FPGA
Heterogeneous Programming
Parallel Programming
Type of item
Thesis
Degree grantor
University of Alberta
Author or creator
Maier, Andrew J
Supervisor and department
Cockburn, Bruce F. (Electrical and Computer Engineering)
Examining committee member and department
Cockburn, Bruce F. (Electrical and Computer Engineering)
Elliott, Duncan (Electrical and Computer Engineering)
Dinavahi, Venkata (Electrical and Computer Engineering)
Department
Department of Electrical and Computer Engineering
Specialization
Computer Engineering
Date accepted
2016-09-30T09:11:04Z
Graduation date
2016-06:Fall 2016
Degree
Master of Science
Degree level
Master's
Abstract
Open Computing Language (OpenCL) is a high-level language that allows developers to produce portable software for heterogeneous parallel computing platforms. OpenCL is available for a variety of hardware platforms, with compiler support being recently expanded to include Field-Programmable Gate Arrays (FPGAs). This work investigates flexible OpenCL designs for the iterative min-sum decoding algorithm for both symmetric and asymmetric Low-Density Parity Check (LDPC) codes over a range of codeword lengths. The computationally demanding LDPC decoding algorithm offers several forms of parallelism that could be exploited by the Altera-Offline-Compiler (AOC version 15.1) for OpenCL. By starting with the recommended design approaches and optimizing based on experimentation, the highest throughput symmetric LDPC decoder produced a maximum corrected codeword throughput of 68.22 Mbps for 32 decoding iterations at the compiler-selected FPGA clock frequency of 163.88 MHz for a length-2048 (3,6)-regular code. Designs for three of the DOCSIS 3.1 [7] standard asymmetric codewords were investigated and implemented using the AOC. The designs prove that OpenCL on FPGAs can produce high-throughput results for industry-sized asymmetric LDPC codes with significantly shorter design time compared to other custom hardware and software applications.
Language
English
DOI
doi:10.7939/R3PZ51V3P
Rights
This thesis is made available by the University of Alberta Libraries with permission of the copyright owner solely for the purpose of private, scholarly or scientific research. This thesis, or any portion thereof, may not otherwise be copied or reproduced without the written consent of the copyright owner, except to the extent permitted by Canadian copyright law.
Citation for previous publication
A. J. Maier, B. F. Cockburn, Implementation of decoders for symmetric low density parity check codes on parallel computation platforms using OpenCL, in: 2016 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE) (CCECE 2016), Vancouver, Canada, 2016, pp. 1176–1181

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Copyright note: © Andrew James Maier 2016
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