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Permanent link (DOI): https://doi.org/10.7939/R30P95

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Theses and Dissertations

Low-Area Low-Power Delta-Sigma Column and Pixel Sensors Open Access

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Other title
Subject/Keyword
Delta-sigma ADC, pixel-level ADC, logarithmic image sensor, column-level ADC, modulator, decimator, low power, low area, fixed-pattern noise, FPN
Type of item
Thesis
Degree grantor
University of Alberta
Author or creator
Mahmoodi, Alireza
Supervisor and department
Joseph, Dileepan (Electrical and Computer Engineering)
Examining committee member and department
Moez, Kambiz (Electrical and Computer Engineering)
Cockburn, Bruce (Electrical and Computer Engineering)
Yang, Herbert (Computing Science)
Nairn, David (University of Waterloo, Electrical and Computer Engineering)
Gaudet, Vincent (Electrical and Computer Engineering)
Department
Department of Electrical and Computer Engineering
Specialization

Date accepted
2011-07-29T18:26:25Z
Graduation date
2011-11
Degree
Doctor of Philosophy
Degree level
Doctoral
Abstract
Delta-sigma analog-to-digital converters (ADCs) are widely used in audio applications, but their use in video applications is emerging. By introducing novel decimator and modulator design flows, this thesis advances the state-of-the-art in delta-sigma data conversion and image sensing. As the approach concerns arrays of many ADCs, it is essential to minimize the layout area and power consumption of each ADC. For maximum scalability, each column or pixel must include a decimator. Conventional decimation, e.g., based on comb filters, is unsuitable for this purpose. Instead, finite-impulse response decimation may be realized efficiently in bit-serial fashion by generating optimal coefficients at the chip-level. As for the modulator, architectural choices and modeling approaches are taken to reduce both area and power while realizing specifications and tolerating mismatch. Very small capacitors suffice to achieve reasonable specifications. These design flows are used with 0.18μm CMOS technology to fabricate specific designs. In a first chip with several data converters, column and pixel-level ADCs achieve figures of merit (150 and 137dB) comparable to state-of-the art delta-sigma ADCs, but with smaller modulator areas (1,850 and 627μm2). In a second chip with two image sensors, logarithmic pixels are combined with column and pixel-level ADCs to make digital video cameras. Both image sensors achieve peak signal-to-noise-and-distortion ratios (35 and 46dB) comparable to the human eye and better than state-of-the-art logarithmic cameras. Although the present results are immediately useful, the approach is also suitable for low-voltage nanoscale CMOS processes, which would further reduce the layout area and power consumption.
Language
English
DOI
doi:10.7939/R30P95
Rights
Permission is hereby granted to the University of Alberta Libraries to reproduce single copies of this thesis and to lend or sell such copies for private, scholarly or scientific research purposes only. Where the thesis is converted to, or otherwise made available in digital form, the University of Alberta will advise potential users of the thesis of these terms. The author reserves all other publication and other rights in association with the copyright in the thesis and, except as herein before provided, neither the thesis nor any substantial portion thereof may be printed or otherwise reproduced in any material form whatsoever without the author's prior written permission.
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