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Permanent link (DOI): https://doi.org/10.7939/R3XW7V

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Parallel-Node Low-Density Parity-Check Convolutional Code Encoder and Decoder Architectures Open Access

Descriptions

Other title
Subject/Keyword
LDPC
Achitecture
throughput
Encoder
VLSI
Decoder
parallelization
Convolutional
energy-per-bit
Type of item
Thesis
Degree grantor
University of Alberta
Author or creator
Brandon, Tyler
Supervisor and department
Elliott, Duncan (Electrical and Computer Engineering)
Cockburn, Bruce (Electrical and Computer Engineering)
Examining committee member and department
Fair, Ivan (Electrical and Computer Engineering)
Gaudet, Vincent (Electrical and Computer Engineering)
Elliott, Duncan (Electrical and Computer Engineering)
Nikolaidis, Ioanis (Computing Science)
Gulak, P. Glenn (Electrical and Computer Engineering)
Cockburn, Bruce (Electrical and Computer Engineering)
Department
Department of Electrical and Computer Engineering
Specialization

Date accepted
2010-01-29T17:29:35Z
Graduation date
2010-06
Degree
Doctor of Philosophy
Degree level
Doctoral
Abstract
We present novel architectures for parallel-node low-density parity-check convolutional code (PN-LDPC-CC) encoders and decoders. Based on a recently introduced implementation-aware class of LDPC-CCs, these encoders and decoders take advantage of increased node-parallelization to simultaneously decrease the energy-per-bit and increase the decoded information throughput. A series of progressively improved encoder and decoder designs are presented and characterized using synthesis results with respect to power, area and throughput. The best of the encoder and decoder designs significantly advance the state-of-the-art in terms of both the energy-per-bit and throughput/area metrics. One of the presented decoders, for an Eb /N0 of 2.5 dB has a bit-error-rate of 10−6, takes 4.5 mm2 in a CMOS 90-nm process, and achieves an energy-per-decoded-information-bit of 65 pJ and a decoded information throughput of 4.8 Gbits/s. We implement an earlier non-parallel node LDPC-CC encoder, decoder and a channel emulator in silicon. We provide readers, via two sets of tables, the ability to look up our decoder hardware metrics, across four different process technologies, for over 1000 variations of our PN-LDPC-CC decoders. By imposing practical decoder implementation constraints on power or area, which in turn drives trade-offs in code size versus the number of decoder processors, we compare the code BER performance. An extensive comparison to known LDPC-BC/CC decoder implementations is provided.
Language
English
DOI
doi:10.7939/R3XW7V
Rights
License granted by Tyler Brandon (brandon@ece.ualberta.ca) on 2010-01-28T20:20:26Z (GMT): Permission is hereby granted to the University of Alberta Libraries to reproduce single copies of this thesis and to lend or sell such copies for private, scholarly or scientific research purposes only. Where the thesis is converted to, or otherwise made available in digital form, the University of Alberta will advise potential users of the thesis of the above terms. The author reserves all other publication and other rights in association with the copyright in the thesis, and except as herein provided, neither the thesis nor any substantial portion thereof may be printed or otherwise reproduced in any material form whatsoever without the author's prior written permission.
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