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Permanent link (DOI): https://doi.org/10.7939/R3JK93

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An FPGA-Based Acceleration Platform for The Auction Algorithm Open Access

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Other title
Subject/Keyword
Auction Algorithm
FPGA
Type of item
Thesis
Degree grantor
University of Alberta
Author or creator
Zhu, Pengfei
Supervisor and department
Hua Li, Department of Mathematics and Computer Science, University of Lethbridge
Yu (Bryan) Hu, Department of Electrical and Computer Engineering, University of Alberta
Examining committee member and department
Yu (Bryan) Hu, Department of Electrical and Computer Engineering, University of Alberta
Zhijun Qiu, Department of Civil and Environmental Engineering, University of Alberta
Hua Li, Department of Mathematics and Computer Science, University of Lethbridge
Bruce Cockburn, Department of Electrical and Computer Engineering, University of Alberta
Department
Department of Electrical and Computer Engineering
Specialization
Computer, Microelectronics Devices, Circuits and Systems
Date accepted
2012-09-28T15:32:15Z
Graduation date
2012-09
Degree
Master of Science
Degree level
Master's
Abstract
Auction algorithms have been applied in various linear network problems, such as assignment, transportation, max-flow and shortest path problem. The inherent parallel characteristics of these algorithms are well suited for Field-Programmable Gate Array (FPGA) hardware implementation. In this work, we focus on the acceleration of auction algorithms to solve the assignment problem.
Language
English
DOI
doi:10.7939/R3JK93
Rights
Permission is hereby granted to the University of Alberta Libraries to reproduce single copies of this thesis and to lend or sell such copies for private, scholarly or scientific research purposes only. Where the thesis is converted to, or otherwise made available in digital form, the University of Alberta will advise potential users of the thesis of these terms. The author reserves all other publication and other rights in association with the copyright in the thesis and, except as herein before provided, neither the thesis nor any substantial portion thereof may be printed or otherwise reproduced in any material form whatsoever without the author's prior written permission.
Citation for previous publication
1. Pengfei Zhu, Chun Zhang, Hua Li, Ray C.C. Cheung, and Bryan Hu, “An FPGA-based Acceleration Platform for Auction Algorithm”, 2012 IEEE International Symposium on Circuits and Systems, pp. 1002-1005, May 20-23, 2012.

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